The question researchers keep asking us
When we describe what we are building, people familiar with compound semiconductors ask a version of the same question: why silicon, when indium phosphide (InP) or gallium arsenide (GaAs) have better electro-optic properties? It is a fair question, and the answer is not obvious without tracing through the actual engineering constraints. This post is our attempt to give that answer carefully, without pretending there are no trade-offs.
What III-V materials do better
The term III-V refers to compound semiconductors formed from elements in groups III and V of the periodic table. Indium phosphide and gallium arsenide are the most relevant here. These materials have several optical properties that silicon lacks or has in weaker form.
First, III-V materials have direct bandgaps, which makes them efficient light emitters. Silicon has an indirect bandgap, making on-chip laser integration in silicon extraordinarily difficult. III-V lasers are the dominant laser source technology in photonic communications precisely because of this property.
Second, III-V materials exhibit the Pockels effect (the linear electro-optic effect), which allows a refractive index change proportional to an applied electric field. This enables electro-optic modulators that operate at very high speeds (tens to hundreds of GHz) with relatively low drive voltage. Silicon does not have the Pockels effect in its bulk crystalline form, because silicon has a centrosymmetric crystal structure that forbids a linear electro-optic response. Silicon modulators typically rely on the plasma dispersion effect, where a free-carrier density change (introduced by a PN junction) changes the refractive index. This is effective but has different speed and efficiency characteristics than the Pockels effect.
Third, III-V materials generally have higher optical nonlinearities, which can be useful in certain signal processing architectures.
If you are building a high-speed optical interconnect or a single-chip laser with integrated modulation, III-V is a compelling platform. The optical performance is genuinely better in these specific respects.
The foundry compatibility problem
Silicon photonics does not beat III-V on raw optical metrics. It wins on a different set of criteria that are decisive for a product that needs to be manufactured at scale and at a cost that makes economic sense for a data-center co-processor.
Silicon photonic devices are fabricated in CMOS-compatible foundries using processes that are variants of the well-established silicon semiconductor manufacturing infrastructure. A silicon-on-insulator photonic chip can be designed using a commercial process design kit, taped out to a foundry like IMEC, GlobalFoundries, or Tower Semiconductor, and received back as a tested wafer. The design flow is mature, the minimum feature sizes are controlled at state-of-the-art levels, and the cost per die drops predictably with volume. The same foundry run can integrate electronic circuits alongside the photonic waveguides.
III-V photonic devices require specialized foundries. The process equipment for InP is different from silicon, the wafer sizes are smaller (typically 4-inch or 6-inch wafers rather than 12-inch for silicon), the cost per wafer is substantially higher, and the design flow tooling is less mature. Heterogeneous integration of III-V components onto a silicon substrate (to get the best of both) is an active research area, but it adds a bonding step and yield complexity that is not present in a monolithic silicon process.
For an inference co-processor that needs to reach hundreds or thousands of units at a cost that makes sense relative to a GPU, foundry accessibility is not a minor consideration. It is the path to the product existing.
Modulation speed is not the binding constraint for inference
The argument for III-V modulators is strongest when bandwidth is the binding constraint. In a coherent optical communications system, you want to modulate data at tens of gigabits per second per channel, and the Pockels-effect modulator's speed advantage over a plasma-dispersion silicon modulator is significant.
In a photonic inference chip, the binding constraint is different. We are not modulating a continuous stream of data at maximum bandwidth. We are encoding neural network weights into the phase settings of an MZI array, then running input vectors through the matrix. The weight encoding happens once per model or per batch. The matrix-vector products happen at rates determined by the inference throughput target, which for current large model inference workloads is in the range of thousands to tens of thousands of tokens per second, not terabits per second.
At those rates, the plasma dispersion effect in silicon is fast enough. A PN-junction silicon modulator can easily operate at speeds well above what inference throughput demands. The speed advantage of III-V in this context is not actually needed, so the performance trade-off that makes III-V attractive for communications does not apply with the same force to inference.
Laser integration and the hybrid approach
The one area where the silicon disadvantage is hardest to work around is laser sources. A silicon photonic chip needs a laser input, and that laser cannot be in silicon. The approaches are: off-chip laser with fiber coupling to the silicon chip; bonded III-V laser die on the silicon chip; or a heterogeneously integrated III-V laser processed directly on silicon using wafer bonding techniques.
All three approaches are in use in various silicon photonics products. The industry has converged on treating this as an integration challenge rather than a fundamental barrier. Our current architecture uses an external laser source coupled to the chip through an edge coupler. This is simpler to prototype and iterate, at the cost of some system footprint. The long-term answer for a packaged production chip will involve closer laser integration, and the current state of the art in III-V on silicon bonding makes that feasible, though not trivial.
We are not claiming silicon photonics is the only viable path for photonic inference. If III-V fabrication infrastructure becomes more accessible at lower cost, the trade-off analysis changes. The technology choice we have made reflects the current reality of foundry access, cost, and the specific performance requirements of inference, not a conviction that silicon is always superior for optical computing. For what we are building right now, silicon is the right material to be in.