The moment the metric shifts
In a research lab, a successful result is one that advances understanding. An insertion loss of 1.8 dB on a carefully fabricated test coupler is publishable if it represents a new design technique, even if only three out of ten fabricated devices hit that number. The other seven can be discarded. Yield is irrelevant to the paper.
Production silicon does not work that way. A photonic chip for inference needs to work across every die on a wafer, across wafers in a batch, and across batches separated by months. The metric shifts from peak performance to the 10th percentile of a yield distribution. That shift changes nearly everything about how you design a device.
We came out of an applied photonics research background. The translation from bench result to foundry-compatible design consumed far more engineering effort than we anticipated. This post is an honest accounting of what we ran into.
Design rules are not suggestions
Academic photonics publications routinely report devices fabricated with minimum feature sizes at or below what a commercial process design kit (PDK) allows. The reasoning is sound in a research context: a university fab or a specialized research line can tolerate edge cases. You get one chip back, test it, and publish.
A commercial silicon photonics foundry operates differently. The PDK defines minimum waveguide widths, minimum bend radii, minimum spacing between optical and electrical routing layers, and dozens of other constraints derived from yield statistics gathered over hundreds of wafer runs. Violating these is not a creative tension; it is a path to expensive scrap.
When we ported our initial MZI designs to a commercial 220 nm SOI process, several waveguide taper geometries that we had used in research did not comply with PDK spacing rules. The performance difference in a single-device test was negligible, but foundry DRC (design rule check) would reject the layout outright. Redesigning for compliance cost roughly six weeks of engineering time. The broader lesson: PDK compliance is not a tax on creativity. It is the mechanism by which the foundry guarantees a yield curve. Work within it from the beginning.
Fabrication variation and optical sensitivity
Silicon photonic devices are sensitive to fabrication variation in ways that purely electronic circuits are not. An MZI splits a waveguide, applies a phase shift to one arm, and recombines the two paths. The extinction ratio at the output depends on the path length difference, which is set partly by design and partly by the actual etch depth and sidewall angle of the waveguide rib. Two nominally identical dies on the same wafer will have slightly different MZI responses because the etch uniformity varies across the wafer surface.
In a research context, you characterize each device individually and tune it. In a production context, tuning every MZI on a chip with hundreds of interferometers is not practical if it requires human intervention. The solution is active thermal tuning with closed-loop calibration firmware: small heaters on each phase-shifter arm, driven by an on-chip controller that runs a calibration sweep at startup.
This approach is well-established in silicon photonics for telecom applications, but the inference context adds a constraint: calibration must complete in under a few hundred milliseconds, or it imposes unacceptable initialization latency for an inference co-processor. Getting calibration time under control turned out to be a significant firmware problem, not just an optics problem. The physics of the device and the software architecture of the runtime are tightly coupled in ways that a pure research device never needs to confront.
Packaging rewrites the system loss budget
On a research bench, light enters and exits a photonic chip through fiber-to-chip grating couplers positioned on the chip surface. Coupling loss of 2 to 4 dB per interface is acceptable when you are characterizing a single component and have a tunable laser with plenty of output power.
In a packaged product, the situation differs. The laser source is co-packaged or coupled through a fiber array attached with UV-cure adhesive. The alignment tolerance is tighter. Temperature cycling over the product lifetime stresses the adhesive bond. Grating coupler efficiency varies with polarization and wavelength in ways that a fixed-alignment package must accommodate without human adjustment.
We are not claiming to have solved packaging. We are pre-production and still working through the co-packaging architecture. But packaging is the single place where research-optimized device choices have the most downstream consequences. Optimizing for the chip in isolation, without accounting for how light enters and exits in final assembly, produces a chip that performs well in the lab and poorly in a system.
Reliability tests that research does not require
Research devices are typically used for days to weeks in controlled lab environments. Production silicon must survive temperature cycling from -10 C to 85 C, extended operating hours (JEDEC-style HTOL testing targets thousands of hours), humidity exposure, and mechanical shock. None of these were part of our initial device design criteria.
The most immediate issue in early reliability work is thermo-optic phase shifter degradation over thermal cycles. The metal heater traces experience stress-induced resistance drift, which shifts the calibrated phase setting. The system needs to re-calibrate, and the calibration range needs margin for this drift. Adding that margin means some phase-shifter ranges that were tight in the original design needed to be widened, which increased die area and the power draw of each heater.
We are being transparent about this because the framing that sometimes appears in deep-tech hardware discussions understates the engineering gap between a published result and a qualified product. A result and a product sit at different points on a very long road. We are partway down it, and we think the broader photonic inference community benefits from seeing the terrain honestly.
What transfers cleanly from research
The picture is not all friction. Several things carry forward directly. The physics of the MZI as a multiply-accumulate unit is the same at any scale. Weight-encoding schemes developed in academic photonic neural network research work at the device level. The fundamental energy argument for optical computation does not change with process node.
What the research base provides is a deep understanding of the parameter space: which design knobs matter for performance, which loss mechanisms dominate, which architectural choices are dead ends. That understanding is hard to acquire without the research foundation, and it makes production engineering more directed. We spend less time in the wrong part of the design space because the research literature has already mapped a lot of it.
The translation work is real and time-consuming. But it compounds: each tape-out teaches the foundry process better, each calibration firmware iteration reveals more about the device-software interface, each packaging iteration narrows coupling loss variance. The path from bench result to production chip is not a cliff. It is a long slope, and you can see far enough ahead to keep moving.